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AMD guru says Intel Xeon shared cache inferior | AMD guru says Intel Xeon shared cache inferior |
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| by Stan Beer | |
| Wednesday, 28 June 2006 | |
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According to a senior technical manager at chipmaker AMD, the new dual core Intel Xeon 5100 server processors are not all they're cracked up to be because of a major design drawback. The problem, according to the AMD technical guru, is that the so-called dual core processors share a single memory cache unlike the dual core AMD Opteron processor, which has separate dedicated cache for each core. Michael Apthorpe, senior technical manager for AMD in Australia and New Zealand, an electronics engineer with more than 25 years experience in chip design starting from his days at Mitsubishi Electric, says that any dual core processor design that involves both cores sharing a single memory cache has both performance and power consumption disadvantages. "There are two types of cache with processors and they are known as exclusive and inclusive cache," says Apthorpe. "With inclusive cache, you have one allocation of RAM. What happens is that if you're running a program and all of sudden you change programs, you have to stop and flush the entire cache and reallocate and reload it. That takes clock cycles to do and that's our competitor's product." The difference with AMD's Opteron dual core processor range, according to Apthorpe, is that each core on the processor has its own dedicated cache. "That means with our processors, they never have to stop and ask the cache to flush and wait for it to reload," he says. "Therefore, the processor always has full access to the cache which really speeds things up. "When you go to multiple processors, the problem gets even more pronounced. If you have just one cache and one processor is dominating the cache utilisation and then you get a request on the other processor, the same thing happens. That is it has to stop, flush, reallocate and reload. This all takes clock pulses so again it hamstrings the performance of the system. That's why our competitor has to put so much more cache in their systems because they have to make up for the latency. They port information out of their main RAM into the cache of the processor and they try to make up the latency which they create by stopping, flushing and reloading the processor cache." According to Apthorpe, another drawback of the Intel dual core system is the frontside bus technology. He says: "Their frontside bus is single direction. Therefore you have to load information, wait, come back and unload it. Our system has a bi-directional interface. Therefore, you have no stopping, reflushing and reloading. Thus, with our competitor you have latency with the frontside bus and latency involved with incusive and not exclusive cache." Apthorpe says the Intel Xeon involving large amounts of cache on the processor also has power consumption disadvantages. "Cache is a huge consumer of power, so when you have large amounts of cache you always have large amounts of heat," he says. Aside from performance and power considerations, Apthorpe claims the cache issue for Intel also gives AMD dual core technology a clear cost advantage over Intel. He says: "The cost of manufacturing is the cost of the wafer. At this point in time we're making 300mm wafers. Let's say for instance you can get 100 dies onto a wafer. If you increase the cache from 1 MB to 2 MB, you might only be able to get 75 dies onto that same wafer and, thus your cost per processor has increased dramatically." We will try to track down an Intel guru to get their spin on what is shaping up to be an interesting war of attrition between the incumbent market leader and an aggressive and innovative upstart that is making serious inroads into the processor market. {moscomment}
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